Pat Meaney is a Senior Technical Staff Member and Master Inventor at IBM as the Chief Architect of IBM Z Memory. He was responsible for architecting and delivering the IBM Z RAIM memory subsystem and continues to be the lead architect for IBM Z Memory. Since joining IBM Poughkeepsie in 1986, Pat has held design, timing, and RAS leadership positions on the ES/9021 bipolar-based machines as well as the s390/System Z (Generations 4-15) CMOS systems. Mr. Meaney has achieved a twenty-sixth level patent plateau, holds one hundred nine U.S. patents, and has several patents pending. He has received five Outstanding Technical Achievements Awards, an Outstanding Innovation Award, and an IBM Corporate Award for RAIM Memory. He has also co-authored eleven technical papers on Processor Cache, RAS, and Memory. Pat holds a B.S. in electrical and computer engineering from Clarkson University (1986) and an M.S. in computer engineering from Syracuse University (1991).